Volatile random access memory, such as SRAM or DRAM (or SDRAM) or PSRAM (hereinafter collectively referred to as RAM), are well known in the art. Typically, these types of volatile memories receive address signals on an address bus, data signals on a data bus, and control signals on a control bus.
Parallel NOR type non-volatile memories are also well known in the art. Typically, they receive address signals on the same type of address bus as provided to a RAM, data signals on the same type of data bus as that provide to a RAM, and control signals on the same type of control bus as that provided to a RAM. Similar to a RAM, NOR memories are a random access memory device. However, because NOR memories require certain operations, not needed by a RAM, such as SECTOR ERASE or BLOCK ERASE, the operations, which are in the nature of commands, are provided to the NOR device as a sequence of certain data patterns. This is known as NOR command protocols. In the prior art, there are two types of NOR command protocols: 1) those protocol commands that are compatible with the protocol command set initially promulgated by Intel, and 2) those protocol commands that are compatible with the protocol command set initially promulgated by AMD. In either event, a NOR memory interfaces electrically to the same address, data and control buses as a RAM interfaces with. Furthermore, conventional NOR memory devices may also provide data, address, and control signals serially, in well known conventional formats such as SPI, LPC or firmware hub.
NAND type non-volatile memories are also well known in the art. Unlike parallel NOR devices, however, NAND memories store data in random accessible blocks in which cells within a block are stored in a sequential format. Further, address and data signals are provided on the same bus, but in a multiplexed fashion. NAND memories have the advantage that they are more dense than NOR devices, thereby lowering the cost of storage for each bit of data.
Because of the lower cost per bit of data for a NAND device, there has been attempts to use a NAND device to emulate the operation of a NOR device. One such device called OneNAND (trademark of Samsung Corporation) uses a RAM memory to temporarily buffer the data to and from a NAND memory, thereby emulating the operation of a NOR memory. However, it is believed the OneNAND device suffers from two shortcomings. First, it is believed that the user or the host device which interfaces the OneNAND must keep track of the data coherency. In data coherency, because the user or host writes to the RAM, the data in the RAM may be newer (and therefore different from the) data in the location in the NAND from which the data in the RAM was initially read. Thus, in the OneNAND device the user or the host must act to write data from the RAM back to the ultimate location in the NAND to store that data, or to remember that the data in the RAM is the newer data. A second problem is believed to be a shortcoming of the OneNAND device is that it cannot provide for automatic address mapping. In the OneNAND device, once data is written into the RAM portion of the OneNAND device, the host or the user must issue a command or series of commands to write the data in the RAM portion to the ultimate location in the NAND portion of the OneNAND device. Similarly, for a read operation, the host or user must issue a read command from specified location(s) in the NAND portion of the OneNAND to load that data into the RAM portion, and then read out the data from the RAM portion.
Another prior art device that is believed to have similar deficiency is the DiskOnChip device from M Systems. In the DiskOnChip device, a thin controller with a limited amount of RAM controls the operation of NAND memories. However, it is believed that the controller portion of the DiskOnChip device does not have any on board nonvolatile bootable memory, such as NOR memory.
A prior art publication showing the use of NAND memories with a controller emulating NOR memory operation is shown in US patent application 2006/0053246, published Mar. 9, 2006. Although this publication shows the use of NAND memories with controller connected to a plurality of processors, it appears that the NAND memory cannot be accessed directly through an ATA format operation. Thus, all access to the NAND memory must be accomplished by the controller with no direct access from the external.
Computer systems are well known in the art. In particular, a computer system adhering to the “IBM PC” standard is well known in the art. Referring to FIG. 6, there is shown a computer system 300 of the prior art. The computer system 300 conforms to the “IBM PC” architecture. The system 300 comprises typically a motherboard 312 on which are mounted a variety of components such as a processor 314, such as a Pentium microprocessor made by Intel Corporation, a memory controller hub chip 316, also known as Northbridge chip 316 and a IO controller hub chip 318, also known as Southbridge chip 318. The Northbridge 316 and the Southbridge 318 are known as chipsets and can be obtained from Intel Corporation. Finally, the motherboard 312 comprises a BIOS 320 which is typically a NOR type non-volatile memory device, which is connected to the Southbridge 318 via a bus 350. The bus 350 is also connected to other components of the system 300, such as Hard Disk Drive (HDD) 326, Modem 328, USB or other ports 327, speaker 325, Keyboard 322 and mouse 324. The foregoing system is described and is disclosed in U.S. Pat. No. 6,421,765. See also U.S. Pat. No. 6,330,635.
In the operation of the computer system 300, the processor 314, boots up from the code that is initially stored in the BIOS 320. Once the processor 314 has executed the initial code from the BIOS 320, it sends signals to the HDD 326 to retrieve further code/data stored on the HDD 326. Thereafter, the operation continues.
As can be seen from the foregoing, if the drive 326 is activated, the processor 314 and the entire system 300 must be “on.” With battery time on a lap top computer 300 at a premium, it is desired to conserve battery power. Further, it is desired to improve the performance of such a system 300. Accordingly, there is a need for an improved device that can satisfy the foregoing.